1000-V 9.1-$\hbox{m}\Omega \cdot \hbox{cm}^{2}$ Normally Off 4H-SiC Lateral RESURF JFET for Power Integrated Circuit Applications

Abstract

A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> of 1028 V and a specific on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on-sp</sub> of 9.1 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> has been experimentally demonstrated. The device has a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">br</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on-sp</sub> figure-of-merit of 116 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The fabricated double-RESURF devices have a vertical channel length of 1.8 mum, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 mum. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated