Circuit partitioning for huge logic emulation systems

Abstract

Article Free Access Share on Circuit partitioning for huge logic emulation systems Authors: Nan-Chi Chou Cadence Design Systems, 2655 Seely Rd. MS 6B1, San Jose, CA Cadence Design Systems, 2655 Seely Rd. MS 6B1, San Jose, CAView Profile , Lung-Tien Liu Computer Science and Engineering, University of California, San Diego, La Jolla, CA Computer Science and Engineering, University of California, San Diego, La Jolla, CAView Profile , Chung-Kuan Cheng Computer Science and Engineering, University of California, San Diego, La Jolla, CA Computer Science and Engineering, University of California, San Diego, La Jolla, CAView Profile , Wei-Jin Dai Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CAView Profile , Rodney Lindelof Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CAView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994Pages 244–249https://doi.org/10.1145/196244.196365Published:06 June 1994Publication History 45citation268DownloadsMetricsTotal Citations45Total Downloads268Last 12 Months25Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF