2002 · 203 citations · 15 references
EngineeringComputer EngineeringComputer ScienceCompilersComputer ArchitectureEmbedded SystemsPerformance ModelingPerformance OptimizationPower EstimationPower ManagementPower OptimizationProcessor MicroarchitectureCompiler DesignCompiler-driven Power ReductionEnergy ConsumptionHigh PerformanceMicroarchitectural Power EstimationProcessor Power EstimationRisc ArchitecturesSoftware-level Power Optimization
A software energy estimation model is presented for a family of high‑performance, integrated, 32‑bit embedded RISC processors. The model incorporates factors such as operating frequency, source/destination registers, and operand values, and is used to evaluate previously proposed optimizations for potential energy savings. The model, which is significantly less complex than prior models, predicts energy consumption within 8% with 99% confidence, and the study concludes that a compiler minimizing execution time also minimizes energy consumption for these processors.
A software energy estimation model is presented for a family of high performance, integrated, 32-bit embedded RISC processors. This model is significantly less complex than previous models, and yet is demonstrated to accurately predict energy consumption to within 8% with 99% confidence based on physical measurements. Factors such as operating frequency, source/destination registers, and operand values are explored. In view of this model, previously proposed optimizations are evaluated for potential energy savings. We conclude that, for the class of processors under discussion, a good optimizing compiler that minimizes execution time will simultaneously minimize energy consumption.
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