Processor Power Estimation is a computational modeling technique that quantifies the dynamic and static power consumption of a central processing unit during operation, distinguishing itself from broader system-level power estimation methods by focusing specifically on the microarchitectural and circuit-level behaviors of the processor core.
279
Publications
19.5K
Citations
779
Authors
233
Institutions
Publications per year
2017–2026
36
Parents
Publications
279
1–5 of 279
Authors
779
- MM
11
h-index
- DS
10
h-index
- CS
8
h-index
- VZ
6
h-index
- DB
6
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1–5 of 779
Institutions
233
Princeton University
Princeton, United States
20 h-index
58 publications
16.7K citations
Intel (United States)
Santa Clara, United States
12 h-index
45 publications
2.8K citations
The University of Texas at Austin
Austin, United States
11 h-index
29 publications
1.9K citations
Politecnico di Milano
Milan, Italy
10 h-index
34 publications
1.1K citations
IBM (United States)
Armonk, United States
8 h-index
33 publications
1K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
7 h-index
29 publications
1.9K citations
Université de Bretagne Sud
Lorient, France
7 h-index
20 publications
591 citations
Pennsylvania State University
State College, United States
6 h-index
19 publications
899 citations
1–8 of 233
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
13 publications · 556 citations
13
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
9 publications · 1.5K citations
9
h-index
- IEEE Transactions on Computers
7 publications · 509 citations
7
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- IEEE Micro
6 publications · 674 citations
6
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- ACM Transactions on Embedded Computing Systems
TECS · 4 publications · 80 citations
4
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1–5