Compiler-Driven Power Reduction is a power optimization technique in which the compiler analyzes and transforms program code during compilation to minimize energy consumption in the target hardware through architectural-aware scheduling, resource allocation, and instruction-level optimizations.
135
Publications
4.9K
Citations
337
Authors
113
Institutions
Publications per year
2017–2026
8
Parents
Publications
135
1–5 of 135
Authors
337
- MK
15
h-index
- MI
11
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- FL
8
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- NV
8
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- UKUlrich Kremer
Rutgers, The State University of New Jersey, United States
6 publications · 557 citations
6
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1–5 of 337
Institutions
113
Pennsylvania State University
State College, United States
16 h-index
87 publications
2.7K citations
Princeton University
Princeton, United States
6 h-index
17 publications
1.5K citations
Intel (United States)
Santa Clara, United States
6 h-index
15 publications
258 citations
Rutgers, The State University of New Jersey
New Brunswick, United States
5 h-index
11 publications
792 citations
Northwestern University
Evanston, United States
5 h-index
11 publications
195 citations
University of California, Irvine
Irvine, United States
4 h-index
13 publications
653 citations
University of Virginia
Charlottesville, United States
4 h-index
8 publications
308 citations
Seoul National University
Seoul, South Korea
4 h-index
7 publications
145 citations
1–8 of 113
Venues
- ACM SIGPLAN Notices
7 publications · 392 citations
7
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- ACM Transactions on Embedded Computing Systems
TECS · 5 publications · 131 citations
5
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- ACM Transactions on Design Automation of Electronic Systems
TODAES · 4 publications · 139 citations
4
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- International Conference on Computer Aided Design
Conference · 3 publications · 41 citations
3
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- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3 publications · 87 citations
3
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1–5