3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

Abstract

This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> . This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology. Promising results in term of density and stability using TCAD simulations are shown for a 4T SRAM load-less cell.