2009 · 27 citations · 6 references
EngineeringMaterials EngineeringMaterials SciencePolymer EngineeringPolymer MaterialsSemiconductor DevicesFabrication MaterialsPolymer Thin Films3D IntegrationElectrical PropertiesHole FillingPolymer PackagingSilicon WafersThree-dimensional IntegrationThrough-silicon Via PackagingThrough-silicon Vias
In this paper, we present some process developments and polymer material evaluations done to achieve the complete filling of 3D-WLP via. The test wafers used for these studies were either blankets with several via sizes specifically designed to determine via filling process window, or wafers with patterns and stacking which result from a real set-top box demonstrator. Initially, the 3D-WLP integration scheme of the demonstrator which required complete via filling is presented. Then the different test structures and patterns needed to characterize via filling behavior are described. Two methods for via filling are exposed and discussed: spin-on process of liquid polymers and vacuum assisted lamination of dry film resists. Some results concerning filling morphology with dedicated polymers are presented for both methods. After that, the defined set of chemical, mechanical and electrical properties chosen to select the polymers is given and explained. Finally, some materials which fulfill previously defined requirements are evaluated and characterized.
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Integration of a temporary carrier in a TSV process flow
Jean Charbonnier, S. Chéramy, David Henry et al. · 2009 · 61 citations
Facilitating Ultrathin Wafer Handling for TSV Processing
A. Jouve, Shelly Fowler, Mark Privett et al. · 2008 · 42 citations
3D integration technology for set-top box application
David Henry, S. Chéramy, Jean Charbonnier et al. · 2009 · 17 citations
Engineering, Electrical Engineering, Computer-integrated Manufacturing +16