Package stacking in SMT for 3D PCB assembly

Abstract

The need for continued miniaturization, functional densification and integration in handheld electronics products provides the strong incentive for printed circuit board (PCB) assembly in three-dimensions (3D). One way to accomplish 3D assembly is through the use of die stacking in chip scale packages (CSP), where the dice are stacked internally in the package. The other way to accomplish 3D assembly is through the use of package stacking. This is the process where two packages are placed on top of each other during the traditional surface mount placement process and then soldered together during the SMT (surface mount technology) reflow. In this paper, package stacking as part of the SMT process is described. The process, materials, and solder joint formation are characterized, and key issues highlighted.