COP: a Crosstalk OPtimizer for gridded channel routing

Abstract

The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design specification. This paper proposes a crosstalk minimization technique based on segment rearrangement for gridded channel routing. The technique repeatedly rearranges horizontal wire segments and/or increase the number of tracks to satisfy the crosstalk constraints. With experiments, we observed that the presented technique is more effective than the track permutation technique.