Scaling trends of the AES S-box low power consumption in 130 and 65 nm CMOS technology nodes

Abstract

In the recent years, the power consumption of the AES (advanced encryption standard) S-box has been a target for intensive optimization as the power budget of security enhanced RFID (radio frequency identification devices) tags is limited to a few muW. In this paper, 0.13 mum and 65 nm CMOS technology nodes are thoroughly investigated in order to select the most appropriate one in terms of power consumption and computation delay. Schematic simulation results of full custom S-boxes show that the optimum choice in our context is the LP (low power) flavor of the 65 nm node with standard V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> (SVT) devices. This leads to a power consumption below 100 nW at 100 kHz using nominal 1.2 V supply voltage, which is an order of magnitude lower than what was previously published in the open literature. The reported delay is 2.35 ns. Our study then extends the reduction of the power consumption further by reducing the supply voltage. The power consumption at 100 kHz decreases by 60 % as the supply voltage is reduced to 0.8 V.