Evaluation of a three-dimensional memory cube system

Abstract

Silicon cubes consisting of 18-20 1-Mb DRAM chips have been fabricated. In the stacking process, the chips are joined by adhesive to form the cube, interconnected by chip metallization processes, and packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1-Mb DRAM memory modules that normally form the card array. Memory tube operation is verified by testing both original and cube memory cards on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines, and PGA substrate were performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>