Investigating the Drain-Bias-Induced Degradation Behavior Under Light Illumination for InGaZnO Thin-Film Transistors

Abstract

This letter investigates the effect of gate/drain bias stress in InGaZnO thin-film transistors under light illumination and in a darkened environment. Drain current-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VG</i> ) as well as capacitance-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) transfer curves are measured to analyze the degradation behavior. The device characteristic exhibits a positively parallel shift after the gate/drain bias stress in the dark. On the other hand, the identical stress performed under light illumination leads to not only a negative shift but also a distortion of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> curve in the off state. Such phenomenon can be attributed to hole-trapping-induced barrier lowering near the drain side after illuminated bias stress.