Pulse jitter and timing errors in RSFQ circuits

Abstract

We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3.5-/spl mu/m, 10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed high-speed measurements of BER in the range from 10/sup -9/ to 10/sup -13/ to be carried out. As a result of these experiments, a new type of thermal-fluctuation-induced digital errors in RSFQ circuits has been identified. These "timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10/sup -13/ at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts).