IEEE Transactions on Circuits & Systems II Express Briefs · 2011 · 50 citations · 9 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsMicrowave EngineeringCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingHigh-frequency Semiconductor DevicesMillimeter-wave CommunicationsRadio-frequency Integrated CircuitsBang-bang ControlClock Jitter ModelingComplementary Metal-oxide-semiconductor DevicesPhase-locked Loop DesignPhase-locked LoopsPhase-locked OscillatorsRf Cmos Design
A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μs without and with the modified bang-bang algorithm, respectively.
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High-speed CMOS circuit technique
Jiren Yuan, C. Svensson · IEEE Journal of Solid-State Circuits · 1989 · 792 citations
Engineering, Computer Engineering, Electrical Engineering +16
Digitally Assisted Analog Circuits
Boris Murmann · IEEE Micro · 2006 · 127 citations
Engineering, Computer Engineering, Electrical Engineering +17