Circuit techniques for 1.5-V power supply flash memory

Abstract

We describe circuit techniques for a Flash memory which operates with a V/sub DD/ of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V/sub DD/ level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V/sub DD/, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.