IEEE Micro · 1988 · 14 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designReal-time SystemsHardware DebuggingInstruction-level ParallelismMicroarchitecture DesignProcessor MicroarchitectureReal-time Systems ArchitectureReal-time Systems DesignDebuggingHardware PipeliningHigh PerformanceMicroarchitectural Performance ModelingMicroarchitecture PerformanceReal-time DebuggingReal-time Processor DesignSystem Architecture Design
The 32-bit TX1 microprocessor, developed to meet the architectural specification of Japan's TRON (The Real-Time-Operating Nucleus) project, has been given a loosely coupled pipeline structure to meet the demands of high-performance systems. The authors discuss the design architecture of the TX1, provide some performance analysis for the design, and describe the debugging feature provided on the processor. Results for several benchmark programs show that the average performance of the TX1 is over 5 MIPS (million instructions per second).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Ken Sakamura · IEEE Micro · 1987 · 53 citations
Architecture of the TRON VLSI CPU
Ken Sakamura · IEEE Micro · 1987 · 52 citations