Microarchitectural Performance Modeling

Microarchitectural Performance Modeling is a formal analytical framework that quantifies the dynamic behavior of processor hardware structures and execution-level events to predict performance outcomes at the instruction and pipeline level.

759

Publications

67.3K

Citations

1.7K

Authors

339

Institutions

Publications per year

2017–2026

69

Authors

1.7K

  1. LE
    Lieven Eeckhout

    Ghent University, Belgium

    36 publications · 3.3K citations

    24

    h-index

  2. DB
    David Brooks

    Harvard University Press, United States

    23 publications · 2K citations

    18

    h-index

  3. DB
    Doug Burger

    The University of Texas at Austin, United States

    19 publications · 7.3K citations

    16

    h-index

  4. JE
    Joel Emer

    Massachusetts Institute of Technology, United States

    16 publications · 1.6K citations

    14

    h-index

  5. LK
    Lizy K. John

    The University of Texas at Austin, United States

    13 publications · 656 citations

    13

    h-index

1–5 of 1.7K

Venues

  1. ACM SIGARCH Computer Architecture News

    43 publications · 7.8K citations

    23

    h-index

  2. IEEE Transactions on Computers

    32 publications · 1.5K citations

    22

    h-index

  3. IEEE Micro

    18 publications · 1.8K citations

    15

    h-index

  4. Computer

    15 publications · 2.6K citations

    15

    h-index

  5. IEEE Computer Architecture Letters

    10 publications · 652 citations

    10

    h-index

1–5