Microarchitectural Performance Modeling
Microarchitectural Performance Modeling is a formal analytical framework that quantifies the dynamic behavior of processor hardware structures and execution-level events to predict performance outcomes at the instruction and pipeline level.
759
Publications
67.3K
Citations
1.7K
Authors
339
Institutions
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2017–2026
69
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759
Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie et al. · 1995 · 3.6K citations · Full text
Computer architecture: a quantitative approach
Martin Shute · Microelectronics Journal · 1993 · 3.4K citations
MiBench: A free, commercially representative embedded benchmark suite
Matthew R. Guthaus, Jeffrey Ringenberg, Daniel Ernst et al. · 2001 · 3.1K citations
The SimpleScalar tool set, version 2.0
Doug Burger, Todd Austin · ACM SIGARCH Computer Architecture News · 1997 · 3.1K citations · Full text
Sheng Li, Jung Ho Ahn, Richard Strong et al. · 2009 · 2.4K citations
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University of Wisconsin–Madison
Madison, United States
34 h-index
110 publications
29.1K citations
Intel (United States)
Santa Clara, United States
28 h-index
111 publications
11K citations
The University of Texas at Austin
Austin, United States
26 h-index
110 publications
12K citations
Carnegie Mellon University
Pittsburgh, United States
22 h-index
67 publications
3.6K citations

Ghent University
Ghent, Belgium
21 h-index
57 publications
5.3K citations

Harvard University Press
Cambridge, United States
17 h-index
46 publications
4.3K citations
University of Michigan
Ann Arbor, United States
17 h-index
63 publications
17K citations
Stanford University
Stanford, United States
16 h-index
48 publications
25.7K citations
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43 publications · 7.8K citations
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32 publications · 1.5K citations
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