2004 · 12 citations · 22 references
EngineeringComputer EngineeringComputer ScienceCompilersComputer ArchitectureHardware-software Co-designControl-flow AnalysisInstruction SchedulingInstruction Set ArchitectureRegister AllocationRun-time ReconfigurationSpeculative ExecutionCompiler SupportCompiler-driven Power ReductionException ManagementMicroarchitectural OptimizationPower-aware CompilationRegister File DesignRegister File Organization
This paper evaluates managing the processor's datapath-width at the compiler level by means of exploiting dynamic narrow-width operands. We capitalize on the large occurrence of these operands in multimedia programs to build static narrow-width regions that may be directly exposed to the compiler. We propose to augment the ISA with instructions directly exposing the datapath and the register widths to the compiler. Simple exception management allows this exposition to be only speculative. In this way, we permit the software to speculatively accommodate the execution of a program on a narrower datapath-width in order to save energy. For this purpose, we introduce a novel register file organization, the byte-slice register file, which allows the width of the register file to be dynamically reconfigured, providing both static and dynamic energy savings. We show that by combining the advantages of the byte-slice register file with the advantages provided by clock-gating the datapath on a per-region basis, up to 17% of the datapath dynamic energy can be saved, while a 22% reduction of the register file static energy is achieved.
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