Register File Design

Register File Design is a hardware architectural methodology that specifies the organization, access mechanism, and storage structure of the register array within a processor's microarchitecture to optimize data access speed and power efficiency.

314

Publications

12K

Citations

887

Authors

207

Institutions

Publications per year

2017–2026

20

Authors

887

  1. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    11 publications · 848 citations

    11

    h-index

  2. WJ
    William J. Dally

    Stanford University, United States

    8 publications · 520 citations

    8

    h-index

  3. RK
    Ram Krishnamurthy

    Intel (United States), United States

    8 publications · 284 citations

    8

    h-index

  4. XL
    Xiaoyao Liang

    Shanghai Jiao Tong University, China

    7 publications · 174 citations

    7

    h-index

  5. KA
    Krste Asanović

    University of California, Berkeley, United States

    7 publications · 415 citations

    7

    h-index

1–5 of 887

Venues

  1. IEEE Journal of Solid-State Circuits

    19 publications · 703 citations

    15

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  2. IEEE Transactions on Computers

    12 publications · 491 citations

    12

    h-index

  3. ACM SIGARCH Computer Architecture News

    10 publications · 365 citations

    10

    h-index

  4. 8

    h-index

  5. 4

    h-index

1–5