Concepedia

Microarchitectural Optimization

Microarchitectural Optimization is a computational technique that enhances program execution efficiency by refining the low-level hardware organization and operational dynamics of a processor’s execution units, instruction pipelines, and data paths within the context of Just-In-Time Compilation.

1.3K

Publications

81.3K

Citations

3.1K

Authors

515

Institutions

Publications per year

2017–2026

168

Parents

Publications

1.3K

In-Datacenter Performance Analysis of a Tensor Processing Unit

Norman P. Jouppi, Cliff Young, Nishant Patil et al. · 2017 · 4.4K citations

, , +17

MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems

1997 · 2.1K citations

, , +17

FFTW: an adaptive software architecture for the FFT

Matteo Frigo, Steven G. Johnson · 2002 · 1.8K citations

, , +14

In-Datacenter Performance Analysis of a Tensor Processing Unit

Norman P. Jouppi, Cliff Young, Nishant Patil et al. · ACM SIGARCH Computer Architecture News · 2017 · 1.3K citations · Full text

, , +17

Trace Scheduling: A Technique for Global Microcode Compaction

Fisher · IEEE Transactions on Computers · 1981 · 1.3K citations

, , +13

1–5 of 1.3K

Authors

3.1K

  1. JE
    James E. Smith

    University of Wisconsin–Madison, United States

    20 publications · 1.4K citations

    18

    h-index

  2. WH
    Wen‐mei Hwu

    University of Illinois Urbana-Champaign, United States

    19 publications · 858 citations

    17

    h-index

  3. YN
    Yale N. Patt

    The University of Texas at Austin, United States

    18 publications · 1.2K citations

    15

    h-index

  4. SM
    Scott Mahlke

    University of Michigan, United States

    16 publications · 876 citations

    15

    h-index

  5. MK
    Mahmut Kandemir

    Pennsylvania State University, United States

    17 publications · 749 citations

    15

    h-index

1–5 of 3.1K

Institutions

515

  1. Intel (United States)

    Santa Clara, United States

    34 h-index

    199 publications

    8.5K citations

  2. University of Wisconsin–Madison

    Madison, United States

    30 h-index

    107 publications

    10.2K citations

  3. Stanford University

    Stanford, United States

    28 h-index

    152 publications

    13.7K citations

  4. Carnegie Mellon University

    Pittsburgh, United States

    28 h-index

    102 publications

    15K citations

  5. University of Illinois Urbana-Champaign

    Urbana, United States

    26 h-index

    155 publications

    8.9K citations

  6. University of Michigan

    Ann Arbor, United States

    25 h-index

    130 publications

    10.3K citations

  7. Hewlett-Packard (United States)

    Palo Alto, United States

    24 h-index

    66 publications

    4K citations

  8. University of California, Berkeley

    Berkeley, United States

    24 h-index

    83 publications

    5K citations

1–8 of 515

Venues

  1. IEEE Transactions on Computers

    38 publications · 3.1K citations

    28

    h-index

  2. ACM SIGARCH Computer Architecture News

    49 publications · 4.1K citations

    28

    h-index

  3. ACM SIGPLAN Notices

    41 publications · 1.7K citations

    20

    h-index

  4. IEEE Micro

    29 publications · 1.8K citations

    20

    h-index

  5. arXiv (Cornell University)

    Repository · 17 publications · 911 citations

    15

    h-index

1–5