IEICE Electronics Express · 2009 · 41 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksSystem-on-chip DesignCpu SchedulingHardware AccelerationHeuristic SearchLatency OptimizationNetwork-on-chip DesignProcessor Core DesignEnergy ConsumptionExecution Time AnalysisHardware MappingHardware SchedulingMapping AlgorithmsNetwork-on-chip ArchitecturesPlacement AlgorithmsVideo Object
In this paper, a heuristic mapping algorithm which maps tasks, using priority lists and the crinkle moving pattern is proposed. To evaluate this algorithm, a set of real (i.e. Video Object Plan Decoder) and random applications have been used and the results have been compared. By reducing the number of hops between IP cores, the energy consumption and the completion time of the application (time which all tasks in the task graph execute wholly) have been optimized. Compared to other mapping algorithms, the algorithm execution time (due to its low complexity) is considerably lower.
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Key research problems in NoC design
Ümit Y. Ogras, Jingcao Hu, Radu Mărculescu · 2005 · 293 citations