PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch

Abstract

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing ‘000000’ to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than 465 μs and 95 μs, respectively, at 125°C. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.