A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change <formula formulatype="inline"><tex Notation="TeX">${\hbox{Ge}}_{2}\mathchar"707B {\hbox{Sb}}_{2}\mathchar"707B {\hbox{Te}}_{5}$</tex></formula> alloy is presented. Memory cells are bipolar selected, and are based on a <formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox{trench}}$</tex></formula> architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distributions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150<formula formulatype="inline"> <tex Notation="TeX">$\,^{\circ}{\hbox{C}}$</tex></formula> bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{trench}}$</tex> </formula> cell structure. </para>