2007 · 51 citations · 2 references
EngineeringComputer EngineeringLow-power DesignSystem-on-chip DesignCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMemory Hierarchy DesignPower ManagementPower OptimizationCache DesignCmos ScalingLow-power Data Cache DesignScalable Image CompressionScalable Video CodingVideo Compression
A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13mum CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW in encoding 30fps CIF/HD720 video. Compared to the state-of-the-art design for real-time HD720 video encoding, a 49% reduction in gate count and a 61% reduction in internal memory is achieved
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A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications
Yu‐Wen Huang, Tung-Chien Chen, Chen‐Han Tsai et al. · 2005 · 137 citations