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A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications
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2006
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System On ChipElectrical EngineeringContent-aware Dct/idctEngineeringVlsi DesignMultimedia Signal ProcessingVlsi ArchitectureVideo Coding FormatComputer EngineeringComputer ArchitectureMobile ApplicationsBandwidth-sharing Motion EstimationVideo TransmissionPower ConsumptionMpeg4 Sp EncoderPower-aware Design
A 5mW MPEG4 SP encoder is implemented on a 7.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die in 0.18μm CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption