2006 · 32 citations · 0 references
EngineeringComputer EngineeringHardware-software Co-designLow-power DesignSystem-on-chip DesignClock GatingData CompressionEnergy-efficient Embedded SystemsLow-power Digital Circuit DesignPower ManagementPower OptimizationBandwidthEnergy-efficient ProcessingEnergy-efficient Signal ProcessingMobile Video CodingPower ConsumptionPower Consumption OptimizationPower-efficient DesignVideo Compression
A 5mW MPEG4 SP encoder is implemented on a 7.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die in 0.18μm CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption