Plasma-induced gate-oxide charging issues for sub-0.5 μm complementary metal–oxide–semiconductor technologies

Abstract

Gate dielectric charging issues which occurred during the development of IBM’s 200 mm wafer sub-0.5μm 16-Mbyte dynamic random access memory (DRAM) and logic processes are discussed. Using polysilicon conductor antenna structures and fully integrated DRAM test sites, we investigated three reactive ion etching (RIE) processes: SiO2, Si3N4, and polysilicon etch; argon sputter; and tetraethylorthosilicate (TEOS) and silane-based plasma enhanced chemical vapor deposition (PECVD). The most charging-sensitive processes were SiO2 RIE, argon sputter, and phosphorus-doped TEOS-based PECVD. In particular, we show that gate-oxide degradation is caused by gate dielectric tunneling current throughout plasma exposure and that it can be modulated by systematically changing the plasma properties.