Materials science forum · 2009 · 20 citations · 0 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingIon ImplantationSemiconductor Device MaterialsSemiconductor InterfacesSemiconductor ReliabilityActivationCarrier ConcentrationGate Oxide InterfacesHall ConductivityHall EffectSilicon Carbide (Sic) MaterialsThreshold VoltageThreshold Voltage Extraction
The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.