Model for the charge trapping in high permittivity gate dielectric stacks

Abstract

The generation of traps in SiOx/ZrO2 and SiOx/TiO2 gate dielectric stacks during gate voltage stress of metal-oxide-semiconductor capacitors is investigated. The voltage and temperature dependence of the trap generation rate is extracted from the analysis of the gate current increase observed during the electrical stress. These data can be explained by a model based on a two-stage degradation process, i.e., (1) H+ proton generation in the high permittivity gate dielectric layer by the injected electrons and (2) transport of the H+ protons in the high permittivity material, resulting in bond breaking and trap generation. The threshold electron energy for H+ generation and the activation energy for H+ transport and bond breaking are extracted from fits to the experimental results.