Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs

Abstract

Lateral size effects on surface-roughness-limited mobility in silicon-nanowire FETs are analyzed by means of a full- quantum 3-D self-consistent simulation. A statistical analysis is carried out by considering different realizations of the potential roughness at the Si-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfaces. Nanowires with lateral section varying from 3 times 3 to 7 times 7 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are considered. Effective mobility is computed by evaluating the electron density in a reduced channel region to eliminate parasitic effects from contacts. It is found that transport in wires with the smallest section is dominated by scattering due to potential fluctuations, resulting in a larger standard deviation of the effective mobility, whereas it is dominated by transverse-mode coupling in wires with larger section, resulting in a stronger influence of surface roughness at high gate voltages.