PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Massimo Alioto · IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 180 citations

Electrical Engineering, Engineering, Vlsi Design +12

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era

Swaroop Ghosh, Kaushik Roy · Proceedings of the IEEE · 2010 · 179 citations

Non-volatile Memory, Resiliency Techniques, Engineering +23

Interests and Limitations of Technology Scaling for Subthreshold Logic

David Bol, Renaud Ambroise, Denis Flandre et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 160 citations

Low-power Electronics, Logic Synthesis, Electrical Engineering +13

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Ramesh Vaddi, Sudeb Dasgupta, Rajesh Agarwal · IEEE Transactions on Electron Devices · 2010 · 104 citations

Engineering, Vlsi Design, Nm Cmos +16

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation

Ik‐Joon Chang, Sang Phill Park, Kaushik Roy · IEEE Journal of Solid-State Circuits · 2010 · 83 citations

Engineering, Vlsi Design, Energy Efficiency +17