2010 · 20 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCachingDynamic Power ReductionEmbedded Memory BlocksLow-power Cache DesignMemory Subsystem DesignPower ManagementCache ArchitectureCache DesignCache Dynamic Power ReductionCache Memory DesignEnergy-efficient Memory DesignLow-power Data Cache DesignOn-chip Memory DesignSense Amplifier Design
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7¿ high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (¿SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
2
Scaling deep trench based eDRAM on SOI to 32nm and Beyond
G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations
Engineering, Computer Engineering, Electrical Engineering +17