Abraham Mathews

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

J. Barth, Kavita Nair, Nianzheng Cao et al. · IEEE Journal of Solid-State Circuits · 2010 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache

J. Barth, Don Plass, Erik Nelson et al. · 2010 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Peter J. Klim, J. Barth, W. Reohr et al. · IEEE Journal of Solid-State Circuits · 2009 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +17

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology

Rahul Rao, Christopher Gonzalez, Eric Fluhr et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 11 citations

Engineering, Computer Engineering, Computer Science +12