Future trends in wafer scale integration

Abstract

The dramatic increase in the functional density of VLSI has been achieved without greatly increasing the chip size. In wafer scale integration, the area of an entire wafer is made available to increase the functional density still further. However, the requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism to achieve finite yield, and nonoptimum nature of the AI/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> transmission line for cross-wafer communication have made WSI noncompetitive with state-of-the-art VLSI and dense multichip hybrid packaging approaches, at least so far. On the other hand, the potential benefits of WSI are great. Chief among them is the greatly increased expected reliability, which is partly due to an all-monolithic system and partly because of the hope that fault tolerance, which is an absolute requirement for WSI fabrication, can be extended to failure tolerance, and thus the ability to reconfigure during systems operation, and perhaps even transparent to it. Pipeline- or bus-oriented logic structures were found to be the most promising for WSI implementation.