Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

Abstract

In this paper a new `via-first' technology which is compatible with CMOS high temperature steps will be presented. This technology is based on filling high aspect ratio trenches with doped polysilicon and thinning the silicon after active device bonding onto a wafer carrier. The initial morphological requirements are described and different designs of TSV are presented. The complete technology for TSV achievement is described in detail and the morphological characterization results are discussed. Finally, electrical results obtained with different vias geometries are presented and compared to initial calculations.