Hotspot detection on post-OPC layout using full-chip simulation-based verification tool: a case study with aerial image simulation

Abstract

OPC (Optical Proximity Correction) improves the feature CD (critical dimension) uniformity and pattern fidelity in general. However, since model calibration only takes CD measurements at optimum exposure dose and best focus condition, the correction result may not be desirable at non-optimum conditions due to significant sub-resolution process distortion. Certain specific patterns are prone to bridging or pinching (we refer this type of location as hotspot in this paper) when process drifts a little from optimum condition. Simulation based full-chip verification became the method of choice for capturing hotspots on post-OPC layouts prior to mask tape-out to save development time and cost. In this paper, a complete simulation and analysis flow using SiVL was experimented to capture hotspots for a 100nm node process. Calibrated process model and multiple optical models with different focus/threshold conditions were applied for simulation. The method and effectiveness of filtering and analyzing fatal errors from output error database was discussed. The analysis results were then correlated to actual wafer printing. A good match between prediction and experiment was found.