A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Abstract

Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE can be used to compensate channel distortion, its power dissipation reduces link energy efficiency, which is vitally important in complex systems. One way of reducing DFE power consumption is to use current-integrating summers. Previously published current-integrating DFEs operating above 5 Gb/s were demonstrated on simple test chips lacking support circuitry for CDR and DFE adaptation functions. The architecture presented here includes additional data paths based on current-integrating summers to realize a fully integrated RX with CDR and continuous DFE adaptation. The design also features a digital calibration loop for setting the summer bias currents so that high performance is achieved over process variations and different data rates.