A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver

Abstract

A 7Gb/s 2-tap current-integrating DFE implemented in a 90nm CMOS process is presented. Low power dissipation (9.3mW) is achieved by replacing resistively loaded analog current summers with resettable integrators. With 7Gb/s PRBS-7 data, the input sensitivity is 61 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp-diff</sub> , and the DFE equalizes a 16-inch backplane with 45% horizontal eye opening. The DFE core (integrators, latches, clock buffers) occupies 85 times 65mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .