Cost and benefit models for logic and memory BIST

Abstract

Article Free Access Share on Cost and benefit models for logic and memory BIST Authors: Juin-Ming Lu Lab. for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC Lab. for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROCView Profile , Cheng-Wen Wu Lab. for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROC Lab. for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013, ROCView Profile Authors Info & Claims DATE '00: Proceedings of the conference on Design, automation and test in EuropeJanuary 2000 Pages 710–714https://doi.org/10.1145/343647.343900Published:01 January 2000Publication History 19citation296DownloadsMetricsTotal Citations19Total Downloads296Last 12 Months41Last 6 weeks19 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF