Memory cell and technology issues for 64- and 256-Mbit one-transistor cell MOSD DRAMs

Abstract

The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, storage capacitance and area, leakage current, and on-current. These requirements are based on an analysis and assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference, and bit line capacitance. Pivotal issues specific to the DRAM are identified. It is concluded that sufficient progress will be made so that 64-Mb DRAMs will be successfully produced in the early to mid-1990s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>