Automated, retargetable back-annotation for host compiled performance and power modeling

Abstract

With traditional cycle-accurate or instruction-set simula-tions of processors often being too slow, host-compiled or source-level software execution approaches have recently be-come popular. Such high-level simulations can achieve or-der of magnitude speedups, but approaches that can achieve highly accurate characterization of both power and perfor-mance metrics are lacking. In this paper, we propose a novel host-compiled simulation approach that provides close to cycle-accurate estimation of energy and timing metrics in a retargetable manner, using flexible, architecture descrip-tion language (ADL) based reference models. Our auto-mated flow considers typical front- and back-end optimiza-tions by working at the compiler-generated intermediate rep-resentation (IR). Path-dependent execution effects are accu-rately captured through pairwise characterization and back-annotation of basic code blocks with all possible predeces-sors. Results from applying our approach to PowerPC tar-gets running various benchmark suites show that close to native average speeds of 2000 MIPS at more than 98 % tim-ing and energy accuracy can be achieved.