1997 · 40 citations · 8 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignBranch PredictionMicroarchitecture DesignPerformance ModelingPower DissipationPower EstimationProcessor MicroarchitectureCache Miss RateHigh PerformanceMicroarchitectural Power EstimationMicroarchitecture Performance EvaluationPower ModelPower Modeling And EstimationProcessor Power EstimationProgram Synthesis
This paper presents a new approach for estimatingpower dissipation in a high performance microprocessor chip.First, characteristic profile (including parameters such as thecache miss rate, branch prediction miss rate, pipeline stalls,instruction mix, memory references, etc.) is extracted fromapplication programs. Then, mixed integer linear programmingand heuristic rules are used to gradually transform a genericprogram template to into a fully functional program. Thesynthesized program exhibits the same performance and powerdissipation behavior (as characterized by the extracted profile),yet it has an instruction trace orders of magnitude smaller thanthe initial trace. The synthesized program is subsequentlysimulated on a register-transfer level description of the targetmicroprocessor to provide the power dissipation value. Resultsobtained for the Intel's Pentium processor executing standardbenchmark programs show a simulation time reduction by 3-5orders of magnitude.
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Synthesis and optimization of digital circuits
Choice Reviews Online · 1994 · 2.4K citations
Engineering, Computer Engineering, Electrical Engineering +17
Evaluation of architecture-level power estimation for CMOS RISC processors
Toshinori Sato, Y. Ootaguro, M. Nagamatsu et al. · 1995 · 49 citations
Engineering, Computer Engineering, Electrical Engineering +17
Instruction level power analysis and optimization of software
Vikram Tiwari, Sharad Malik, A. Wolfe et al. · 2002 · 48 citations