Publication | Closed Access
Evaluation of architecture-level power estimation for CMOS RISC processors
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Citations
1
References
1995
Year
Unknown Venue
EngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureEfficient DesignPower ElectronicsHardware SecurityCmos Risc ProcessorsPerformance SimulatorParallel ComputingPower-aware DesignPower ManagementPower-aware ComputingElectrical EngineeringComputer EngineeringGate-level SimulatorPower ConsumptionEnergy Management
An evaluation of the architecture-level power estimation simulator, ESP (Early design Stage Power and performance simulator), is presented. With ESP, it is possible to accomplish more efficient design by using the architecture-level and gate-level simulator correctly. The estimation and the actual measured results are very similar. In addition, the accuracy of ESP has been improved by 18.3%.
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