1995 · 49 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignCmos Circuit DesignLow-power Digital Circuit DesignPower EstimationPower ManagementPower OptimizationPower-aware DesignEarly-stage Power EstimationGate-level ModelingGate-level Power EstimationMicroarchitectural Power EstimationPower Modeling And EstimationProcessor Power EstimationRisc ArchitecturesSimulation-based Power Estimation
An evaluation of the architecture-level power estimation simulator, ESP (Early design Stage Power and performance simulator), is presented. With ESP, it is possible to accomplish more efficient design by using the architecture-level and gate-level simulator correctly. The estimation and the actual measured results are very similar. In addition, the accuracy of ESP has been improved by 18.3%.
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