A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM

Abstract

We have successfully developed a 0.602 /spl mu/m/sup 2/ nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM a pair of capacitors on a same node can be nestled close to each other A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602 /spl mu/m/sup 2/. The cell size was reduced to 32% of previous work. Signal window of 600 mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.