Publication | Closed Access
A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology
17
Citations
2
References
1987
Year
Hardware SecurityNon-volatile MemoryElectrical EngineeringSingle TransistorEngineeringAdvanced Packaging (Semiconductors)Flash MemoryComputer EngineeringComputer ArchitectureHigh-density 256-Kb FlashSemiconductor Device FabricationSemiconductor MemoryElectronic PackagingMicroelectronicsOptoelectronicsTriple-polysilicon TechnologyErasable Prom
A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8/spl times/8 /spl mu/m/SUP 2/, even with relatively conservative 2.0-/spl mu/m design rules, a small die size of 5.69/spl times/5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 /spl mu/s/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.
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