High throughput architecture for the Advanced Encryption Standard Algorithm

Abstract

A high throughput architecture is proposed for an efficient implementation of the Advanced Encryption Standard (AES) Algorithm. The presented architecture is adapted for AES encryptor-only as well as integrated AES encryptor/decryptor designs. The SubBytes/InvSubBytes operations are implemented using composite field arithmetic in order to exploit the sub-pipelining advantage within the loop-unrolling methodology. The proposed architecture minimizes the critical path delay through the modification of the SubBytes/InvSubBytes as well as the KeyExpansion modules. Compared to previously reported AES encryptors and integrated AES encryptors/decryptors designs, the proposed architecture provides an efficiency improvement of 61% and 29% respectively.