Loop Pipelining
Loop pipelining is a compiler optimization technique that belongs to the class of loop transformations, specifically characterized by overlapping the execution of successive iterations of a loop to improve instruction-level parallelism and resource utilization in pipelined architectures.
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2017–2026
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Monica S. Lam · ACM SIGPLAN Notices · 2004 · 890 citations
B. Ramakrishna Rau · 1994 · 708 citations · Full text
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
A. Hodjat, Ingrid Verbauwhede · 2004 · 219 citations
B. Ramakrishna Rau · International Journal of Parallel Programming · 1996 · 195 citations
Register allocation for software pipelined loops
B. Ramakrishna Rau, M. Lee, P. Tirumalai et al. · 1992 · 184 citations
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University of California, Los Angeles
Los Angeles, United States
10 h-index
26 publications
1.7K citations

Cornell University
Ithaca, United States
8 h-index
30 publications
849 citations

University of Notre Dame
Notre Dame, United States
7 h-index
15 publications
431 citations
Hewlett-Packard (United States)
Palo Alto, United States
7 h-index
13 publications
1.6K citations
Tsinghua University
Beijing, China
6 h-index
17 publications
613 citations

Imperial College London
London, United Kingdom
6 h-index
17 publications
466 citations

University of Minnesota
Minneapolis, United States
5 h-index
5 publications
189 citations
Seoul National University
Seoul, South Korea
4 h-index
8 publications
178 citations
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9 publications · 375 citations
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3 publications · 934 citations
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TPDS · 3 publications · 152 citations
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