Longest-path selection for delay test under process variation

TLDR

Manufacturing process variation causes a path to be longest when it can attain the maximum delay under some condition, leading to multiple longest paths per net and local defects that further increase delay. The study aims to detect delay faults from local defects and process variation by testing all longest paths through each net. An efficient method is proposed that models path delays with linear functions to capture structural and process correlation, and prunes non‑longest paths to drastically reduce the path set. Experiments on ISCAS circuits show the method reduces the number of longest paths to 1–6 % of the previous best and cuts running time by a factor of 300.

Abstract

Under manufacturing process variation, a path through a net is called longest if there exists a process condition under which the path has the maximum delay among all paths through the net. There are often multiple longest paths for each net, due to different process conditions. In addition, a local defect, such as resistive open or a resistive bridge, increases the delay of the affected net. To detect delay faults due to local defects and process variation, it is necessary to test all longest paths through each net. Previous approaches to this problem were inefficient because of the large number of paths that are not longest. This paper presents an efficient method to generate the set of longest paths for delay test under process variation. To capture both structural and process correlation between path delays, we use linear delay functions to express path delays under process variation. A novel technique is proposed to prune paths that are not longest, resulting in a significant reduction in the number of paths. In experiments on International Symposium on Circuits and Systems (ISCAS) circuits, our number of longest paths is 1-6% of the previous best approach, with 300/spl times/ less running time.