A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Abstract

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over- and underdrive wordlines with output voltage regulation. The die area is 77 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 μs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-chip-packaged with Haswell family Iris Pro™ die to achieve a high-end graphics part, which provides up to 75% performance improvement in silicon, across a wide range of workloads.