EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignCachingLow-power Cache DesignMemory HierarchyMemory Hierarchy DesignMemory Hierarchy OptimizationMemory Subsystem DesignCache DesignCache Energy ModelingCache ManagementCache OptimizationEnergy ConsumptionLow-power Data Cache DesignMulti-level CachingReuse Distance Analysis
Wire energy has become the major contributor to energy in large lower level caches. While wire energy is related to wire latency its costs are exposed differently in the memory hierarchy. We propose Sub-Level Insertion Policy (SLIP), a cache management policy which improves cache energy consumption by increasing the number of accesses from energy efficient locations while simultaneously decreasing intra-level data movement. In SLIP, each cache level is partitioned into several cache sublevels of differing sizes. Then, the recent reuse distance distribution of a line is used to choose an energy-optimized insertion and movement policy for the line. The policy choice is made by a hardware unit that predicts the number of accesses and inter-level movements.
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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
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