Multi-Level Caching is a memory hierarchy design strategy that employs a hierarchical arrangement of multiple cache levels, differing in size, speed, and proximity to the processor, to optimize memory access latency and bandwidth by exploiting the principle of locality.
99
Publications
4.5K
Citations
262
Authors
107
Institutions
Publications per year
2017–2026
16
Parents
Publications
99
Hybrid cache architecture with disparate memory technologies
Xiaoxia Wu, Jian Li, Lixin Zhang et al. · 2009 · 334 citations
Application-level document caching in the Internet
Azer Bestavros, R.L. Carter, Mark Crovella et al. · 2002 · 150 citations
1–5 of 99
Authors
262
- AG
4
h-index
- NK
4
h-index
- JH
4
h-index
- SD
4
h-index
- JL
4
h-index
1–5 of 262
Institutions
107
Universitat Politècnica de Catalunya
Barcelona, Spain
6 h-index
6 publications
557 citations
Stanford University
Stanford, United States
6 h-index
6 publications
327 citations
IBM (United States)
Armonk, United States
5 h-index
5 publications
458 citations
Pennsylvania State University
State College, United States
3 h-index
3 publications
457 citations
University of Washington
Seattle, United States
3 h-index
3 publications
313 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
3 publications
141 citations
University of Calgary
Calgary, Canada
3 h-index
3 publications
140 citations
University of California, Riverside
Riverside, United States
3 h-index
3 publications
137 citations
1–8 of 107
Venues
- ACM SIGARCH Computer Architecture News
5 publications · 231 citations
5
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- IEEE Transactions on Network and Service Management
TNSM · 2 publications · 48 citations
2
h-index
- IBM Journal of Research and Development
2 publications · 41 citations
2
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- arXiv (Cornell University)
Repository · 2 publications · 37 citations
2
h-index
- IEEE Communications Letters
2 publications · 26 citations
2
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1–5